1. Field of the Invention
The present invention relates to a method for connecting conductive lines formed on separate layers with an intervening insulation layer, More particularly, the present invention relates to a method of manufacturing a semiconductor device having a plurality of thin film transistors, such as memories and liquid crystal display devices, and a wiring structure on different layers.
2. Description of the Related Art
The number of thin film transistors (TFTs) integrated in a unit area is a very important parameter in manufacturing a high density and micro-sized semiconductor device or a high resolution liquid crystal display (LCD) device, In order to design a high-capacity memory device or an LCD device with higher resolution than XGA (Extended Video Graphic Array), the number of TFTs per unit area must be increased. Therefore, bus lines connected to the TFTs are squeezed into ever narrower areas. Therefore, the area used to connect the gate line of the TFT to another line must decrease as well.
A conventional method for connecting bus lines formed on separate layers, and a wiring structure formed by the same method, is as follows. FIG. 1a shows the cross-sectional view of the bus lines formed in separate layers using a conventional method. FIG. 1b shows a plan view of the wiring structure formed using the conventional method. FIGS. 2a-2d show the manufacturing process of the same.
A metal layer, such as aluminum or an aluminum alloy, is deposited on a substrate 11. The metal layer is patterned to form a low resistance gate line 15a. The surface of the low resistance gate line 15a can generate a hillock. A metal layer including chromium or molybdenum is deposited on the substrate 11. The metal layer is patterned to form a second-metal gate line 15 covering the low resistance gate line 15a, as shown in FIG. 2a. The second-metal gate line 15 prevents formation of a hillock on the low resistance gate line 15a.
An insulation material, such as silicon oxide or silicon nitride, is deposited on the substrate 11 having the second-metal gate line 15 to form a gate insulation layer 19. A metal layer, such as chromium or a chromium alloy, is deposited on the gate insulation layer 19, as shown in FIG. 2b. The metal layer is patterned to form a source line 35. The source line 35 is connected to a source electrode of a switching element, such as a TFT.
An insulation material, such as silicon nitride or silicon oxide, is deposited on the substrate 11 having the source line 35 to form a protection layer 39. As shown in FIG. 2b, the low resistance gate line 15a and the second-metal gate line 15, and the source line 35 are located on separate layers, with the gate insulation layer 19 positioned between them. The second-metal gate line 15 and the source line 35 should not normally be connected to each other, because they are used for different purposes. However, they need to be connected to each other during some processing steps, in order to protect the substrate from static electricity damage. For example, if a repair line for source line 35 is formed on the same layer of the same material as the second-metal gate line 15, then the source line 35 should be connected to the repair line. In order to connect the source line 35 to the second-metal gate line 15 (or to the repair line on the same layer as the second-metal gate line 15), a gate contact hole 41 and a source contact hole 51 are first formed, as shown in FIG. 2c. The gate contact hole 41 exposes a portion of the second-metal gate line 15 by etching the protection layer 39 and the gate insulation layer 19. The source contact hole 51 exposes a portion of the source line 35 by etching the protection layer 39 covering the source line 35.
A layer of conductive material, such as indium tin oxide (ITO), is deposited on the protection layer 39. The ITO layer is patterned to form a connecting pad 53. The connecting pad 53 connects the second-metal gate line 15 and the source line 35 through the gate contact hole 41 and the source contact hole 51, as shown in FIG. 2d.
In the conventional method for connecting bus lines formed on separate layers, the lines are connected by a third conductive material through the contact holes formed in same plane. Therefore, space for the contact holes must be reserved. Therefore, there is a limitation to manufacturing a higher density semiconductor device using the conventional method. When manufacturing a high density semiconductor device, all building components of the device become smaller and smaller. Thus, the gate lines and the source lines become narrower and narrower. Furthermore, as the number of connecting parts increases, the area needed for connecting hinders higher integration.